As a means for electrically connecting a semiconductor element (hereinafter called a chip) to external leads of a semiconductor device having a plurality of terminals or pins, such as ICs and LSIs, there are known wire bonding and wireless bonding methods. The wire bonding method is a method whereby a bonding wire made of a fine metal such as gold and aluminum and having a 20 to 30 .mu.m diameter, connects a bonding pad on a chip to an external lead. Bonding wire is bound, for example, by means of a thermocompression bonding method, an ultrasonic bonding method, or both the methods. The wireless bonding method is a method whereby a plurality of gold pads on a chip are connected to a plurality of external leads at a time using specific bumps or metal leads. This method is executed by a known tape carrier scheme, flip chip scheme, beam lead scheme, or the like. As well known, in order to protect a chip from contamination or defect by ambient atmosphere, the chip and its peripheral area are sealed with resin.
FIG. 1 is a plan view of a chip of a resin sealed semiconductor having a well known zigzag in-line package (ZIP). Referring to FIG. 1, at the peripheral area of a chip 1, there are formed bonding pads 2, a V.sub.ss potential bonding pad 3, and a V.sub.cc potential bonding pad 4, at positions corresponding to the layout of a lead frame for ZIP. The V.sub.SS potential bonding pad 3 is connected to a V.sub.SS potential connection line 20 of a closed loop formed at the peripheral area of the chip 1. A V.sub.CC potential connection line (not shown) is also formed at the side of the V.sub.SS potential connection line, the detailed description of this line being omitted because it is not closely related to the present invention. As described above, a chip has a number of power supply lines and a number of electrodes (bonding pads) for supplying input/output signals and power sources. A connection line, particularly a power source line, occupies a large area of wiring space, providing one of obstacles against high integration of a semiconductor device.
FIG. 2 is a plan view of a conventional lead frame on which the chip shown in FIG. 1 is mounted. A semiconductor mount section (hereinafter called a bed) 5 is formed at the central area of the frame, and leads are formed externally of the bed. Each lead is comprised by an inner lead 9 directly connected to a bonding pad, and an outer lead 8 integrally formed with the inner lead 9. At the tip of the inner lead 9, there is formed a metal plated layer 9A such as gold and silver. One of the inner leads 9 is used as a V.sub.SS potential lead 10, and another is used as a V.sub.CC potential lead 13.
The bed 5 is suspended by a side section 7 of the lead frame via suspension pins 6. A metal plated layer 5A such as gold and silver is also formed on the surface of the bed 5. Reference numeral 7A represents a hole for transporting the lead frame.
FIG. 3 is a plan view of the finished semiconductor device wherein the chip 1 shown in FIG. 1 and mounted on the lead frame shown in FIG. 2, is sealed with resin and the side section 7 of the lead frame is removed. FIG. 3 is shown as seeing through the resin sealed portion of the semiconductor device. The chip 1 is attached to the bed 5 using mount paste. Next, the bonding pads 2, V.sub.SS potential bonding pad 3, and V.sub.CC potential bonding pad 4, respectively on the chip 1, are connected to leads 9 (10, 13) using bonding wires 11. Thereafter, the chip 1 is sealed with resin 12 such as epoxy resin, and the leads are cut from the side section and bent. In this manner, the resin sealed semiconductor device is formed, with the side section 7 of the lead frame being removed.
FIG. 4 shows another conventional resin sealed semiconductor device of a thin small out-one package (TSOP) type. FIG. 4 is shown as seeing through resin 12. This device has leads extending from two opposite sides, and suspension pins 6 being formed at the other two opposite sides. These points differ from the device shown in FIGS. 2 and 3.
Recently, semiconductor devices such as ICs and LSIs are becoming more and more integrated, so the number of pads on a chip for supplying input/output signals and power sources is increasing greatly. Furthermore, the chip size is becoming more and more reduced, so the design rule is becoming finer. Therefore, the resistance of a connection line becomes high posing a problem of signal noises.
A connection line, particularly a power source line, occupies most of the chip wiring area. This power source line is therefore becoming more and more fine, resulting in noise generation by power source lines in many cases. For example, the chip 1 shown in FIG. 1 has its V.sub.SS potential bonding pad 3 on the A side. Assuming that the pad 3 is connected to the V.sub.SS potential side (ground), the V.sub.SS potential connection line 20 takes a V.sub.SS potential. However, the potential at the B side of the connection line 20 is not V.sub.SS in practice. Since the V.sub.SS potential connection line is made fine because of high integration of the semiconductor device, the resistance of the V.sub.SS potential connection line 20 becomes high. It is a tendency therefore that the potential of the connection line 20 at the B side opposite to the A side becomes higher than V.sub.SS potential. More specifically, if the connection line width becomes equal to or less than about 100 .mu.m, the V.sub.SS potential rises about 0.1 V from 0 V. Accordingly, noises are superposed upon input/output signals within a chip, posing the problem that operation speed cannot be made high.
The above problem can be solved if, for example, the V.sub.SS potential is supplied to both sides of a chip, at the areas near the A and B sides. However, from the viewpoint of package lead frame designs, it is impossible to increase the number of V.sub.SS leads.
As described above, semiconductor devices are becoming more and more integrated, so the design rule is becoming finer. Therefore, the resistance of a connection line becomes high posing a problem of signal noises.